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Phone: 760-525-5308 

 

LINKS

Qualcomm Corporation
Peregrine Semiconductor
IHP Microelectronics
Jazz Semiconductor
Centellax
AMCC 
TSMC Semiconductor 
MOSIS 
International Trade Commission
U.S. Patent and Trademark Office
Commnexus San Diego
IEEE consultant data base 
IEEE Solid State Circuits Society 
http://www.ieee.org/
http://www.ieeeusa.org/
http://www.ieeeconsultants.com/
RF Cafe
Picture of the Day

 

DESIGN specialists in IC design of mixed signal circuits, including Phase-Locked Loops, VCO, ADC, DAC, DDS, Synthesizers, Sigma-Delta, SONET and other analog high speed blocks. Over 40 years of combined experience designing mixed signal and high-speed analog integrated circuits with state-of-the-art commercial technologies: Bicmos (SiGe), SOS, CMOS and GaAs. Lead designs for numerous commercially available products that include RF Transceivers, Synthesizers, and 2.5, 10 and 40 Gb/s mixed signal ICs. Strong DSP background.


  • Phase Locked Loop - CDR, Synthesizer
  • Delay Locked Loop - DLL, Interpolation
  • Serdes (Serializer and deserializer)- Sonet
  • Digital to Analog - high speed
  • Analog to Digital Converters - including Sigma Delta
  • Direct Digital Synthesizers - DDS
  • Voltage Controlled Oscillators
  • Current Mode Logic in CMOS

SUMMARY OF RECENT ACTIVITIES
Line of OC-768 (40Gbps) multiplexor/demultiplexor with clock recovery, including Bit Error Rate test IC, using 120GHz Silicon Germanium (SiGe) BICMOS 0.25u process, with Direct Digital Synthesizer, Fractional-N Delta-Sigma PLL, and 10 GHz 10-bit DAC.

Numerous other chips include 40G dividers, TIA, Laser driver, TWA, Limiting Amplifier, LNA, Mixer, IQ modulator, VCO's up to 45GHz, and 15 GHz accumulators.


CDR functions in 0.25um through 0.13um CMOS for fiber communications at 2.5Gb/s and 10Gb/s. VCO design and architectures for PLL and data recovery.


Design, layout and test of many integrated circuits for RF in BICMOS on SOI.


2.5 GHz PLL/CRU, and mux/demux functions up to 5 GHz, using 13 GHz bipolar process. Delay Locked Loop (DLL) ICs that had resolution better than 100 pS. MSI circuit for timing delay adjustment, having a resolution of 40 pS.


ATE products in ATT CBICU complementary bipolar process. 275 MHz monolithic PLL and Bipolar RAMDAC.


Combination A/D and D/A converter for sub-ranging hybrid product. Sample-hold, current mode amplification and characterization of both ADC and DAC. 75 MHz reduced power 8-bit A/D converter IC.


Monolithic Microwave Integrated Circuit (MMIC) 6-to-18 GHz amplifiers in GaAs, including hybrid. S-parameter modeling of transistors.

Participation in several start-ups from the beginning, including recruitment and setting up the design tools. Recent work on SOS and photonics. Expert witness experience in patent litigation in PLL and VCO. 

SERVICES include product design, layout, fab interfacing, product characterization, technical marketing; and patent consulting. 


DIVRESI0.GIF



PUBLICATIONS

      Email:germang@ieee.org

DIVRESI0.GIF

 


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